1. Field of the Invention
The present invention generally relates to computer systems, and more specifically to a method of eliminating contention between two or more devices which use a common communications medium, particularly a bus for carrying control signals, wherein the devices (microprocessors) use tri-state drivers to avoid bus contention.
2. Description of Related Art
Modern electronic circuits use many different types of logic components (processing units) to carry out numerous functions. These circuits require a multitude of conductive pathways, or buses, to provide communications or connectivity between the logic components. A communications bus (wire) may be used to transmit data such as values used by a computer program, or program instructions, and further may be used to transmit various control signals. Buses can be unidirectional, bidirectional, or broadcast (used to interconnect three or more devices and allow simultaneous or sequential access to information or controls conveyed on the bus). These buses may be external, e.g., laid out on a printed circuit board, and interconnecting two or more devices which are separately packaged. They may also be internal, interconnecting two or more devices which are fabricated in a single package, such as an integrated circuit (IC).
Buses are used to interconnect devices for a wide variety of applications, including communications between complex computer components such as microprocessors, application specific integrated circuits (ASICs), peripheral devices, random-access memory, etc. Operational demands on buses for computer systems have especially increased with the advent of high-speed computer processors, e.g., those operating at frequencies around 100 MHz or more, and especially above 1 GHz. For example, one problem that is exacerbated at these higher speeds is bus contention, which can occur when two or more logic units attempt to simultaneously access a single bus. If two devices simultaneously drive a bus, the transmitted information becomes garbled and unreliable.
One prior art technique for avoiding bus contention is to provide a tri-state driver, that is, a driver which provides inactive (low or zero) and active (high or one) states, as well as providing an intermediate, high-impedance state (Hi-Z). This technique is implemented, for example, in the bus architecture of PowerPC.TM. microprocessors (PowerPC is a trademark of International Business Machines Corp.). These processors are particularly adapted for use in a symmetric multi-processor (SMP) computer, wherein all of the central processing units are generally identical, and use a common set or subset of instructions and protocols to operate. In the 60X series implementation of the PowerPC.TM. processor, tri-state drivers are used on several different buses to provide control signals between the central processing units. One such signal is the retry signal (ARTRY.sub.--), used as a common control signal for a variety of functions.
The ARTRY.sub.-- signal is an open drain signal (multiple devices can drive the same signal at the same time) but, due to the definition of its functionality and the high bus speeds involved, the communications architecture cannot rely upon resistive pull-up to restore these signals, i.e., from the active (asserted) state, to the inactive (negated) state. Therefore, in order to avoid bus contention when an attempt is made to simultaneously drive the signal by multiple devices, the 60.times. architecture defines the waveform of ARTRY.sub.-- as shown in FIG. 1A (the ratio of CPU clock to bus clock is 1 to 1 in this embodiment). When ARTRY.sub.-- is to be switched by a device from "0" to "1", it must be in the Hi-Z state before it can switch to "1". The specification further requires that each unit restore the signal to a high impedance state. Due to the different bus clock ratios and the restoring nature of this signal, the internal enable signal generally requires more levels of gating logic before it arrives at the input/output (I/O) driving cell, relative to the data path.
FIG. 2 shows a simplified schematic diagram that indicates how the prior art would typically implement the foregoing logic. Two signals, a latch output signal (artry.sub.-- out) and an enable signal (artry.sub.-- en) are used to control the output of an amplifier (driver) 1 which is connected to the ARTRY.sub.-- bus. Signal artry en is generated by the gating logic 2 which is responsive to restoring logic. Signal artry.sub.-- out is generated by a latch 3 which is set by internal control logic which detects any one of a defined set of conditions to which ARTRY.sub.-- must be asserted. The output of latch 3 is further provided as an internal signal (artry.sub.-- out.sub.-- internal) which is used for monitoring the detection of the ARTRY.sub.-- condition, and subsequent assertion of the external ARTRY.sub.-- signal, by the internal logic. The output of driver 1 is also connected to a receiver 4 whose output further provides an input signal (artry.sub.-- in) which is used by the internal logic to detect an ARTRY.sub.-- assertion by some other external bus agent.
The 603 and 604 processors, as well as bridge chips such as the MPC105 and MPC106, all use structures similar to that shown in FIG. 2. This design, however, suffers a serious drawback relating to false switching. False switching can easily occur with devices that use open drain, complementary metal-oxide semiconducting (CMOS) drivers, particularly if there is imperfect synchronization of the multiple drivers attached to the bus. A timing delay is indicated in the timing diagram of FIG. 1B, wherein the foregoing approach is used, to give an example of a "glitch" occurring (the circled spike in FIG. 1B). As seen in FIG. 1B, if the enable signal (artry.sub.-- en) has slightly more delay than the output signal (artry.sub.-- out), then when ARTRY.sub.-- is switching from "0" to "Z", there is a short period of time it can go to "1". This condition may result in bus contention when multiple devices are switching the signal from active to Hi-Z, even though it may be just a very short period of time, effectively nullifying the benefits of a tri-state driver during such a condition.
A simple delay to the artry.sub.-- out signal will not suffice to solve this problem. As seen in the timing diagram of FIG. 1C, if the artry.sub.-- out signal is delayed, it merely shifts the spike when false switching occurs. It would, therefore, be desirable and advantageous to devise an improved tri-state driver for a multiple user bus which ensures that false switching does not result in bus contention.